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| MDS108 Unmanaged 9-Port 10/100 Mbps Ethernet Switch Data Sheet Features * * 8 10/100 Mbps auto-negotiating RMII ports 1 10/100 Mbps auto-negotiating MII/serial port (port 8) that can be used as a WAN uplink or as a 9th port Operates stand-alone or can be cascaded with a second MDS108 to reach 16 ports * * * * XLink expansion MII port (port 8) Operates at 100/200/300/400 Mbps * * * * Default mode allows operation without external EEPROM November 2003 Ordering Information MDS108AL 208 Pin PQFP * -40C to +85C Input ports are defined to be high or low priority Allows explicit identification of IP phone ports External I2C EEPROM for power-up configuration Supports both full and half duplex ports Ports 0 & 1 can be trunked to provide a 200 Mbps link to another switch or server Port 7 can be used to mirror traffic from the other 7 ports (0-6) Utilizes a single low-cost external pipelined, SyncBurst SRAM (SBRAM) for buffer memory 256 KB or 512 KB (1 chip) Provides back-pressure for half duplex 802.3x flow control for full duplex Flow control capabilities - Up to 8 port-based VLANs Full wirespeed layer 2 switching on all ports (up to 2.679 M packets per second) Internal 1 K MAC address table Auto address learning Auto address aging * * Leading-edge Quality of Service (QoS) capabilities provided based on 802.1 p and IP TOS/DS field 2 queues per output port Packet scheduling based on Weighted Round Robin (WRR) and Weighted Random Early Detection/Drop (WRED) With flow control disabled, can drop packets during congestion using WRED 2 levels of packet drop provided * * * * Supports external parallel port for configuration updates Special power-saving mode for inactive ports Ability to support WinSock 2.0 and Windows2000 smart applications Transmit delay control capabilities Assures maximum delay (< 1 ms) Supports mixed voice/data networks * Provides port-based prioritization of packets on up to 4 ports * Optimized pin-out for easy board layout Figure 1 - System Block Diagram 1 Zarlink Semiconductor Inc. Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2003, Zarlink Semiconductor Inc. All Rights Reserved. MDS108 Description Data Sheet The MDS108 is a fully integrated 9-port Ethernet switch designed to support the low-cost requirements of unmanaged switch applications. The MDS108 provides features that are normally not associated with plug-andplay technology, while not requiring an external processor to facilitate their utilization. The MDS108 begins operating immediately at power-up, learning addresses automatically, and forwarding packets at full wire-speed to any of its eight output ports or the XLink expansion port. The default configuration allows operation without using an external EEPROM. With an EEPROM to configure the device at power-up, the MDS108 provides flexible features: port trunking, port mirroring, port-based VLANs and (QoS) capabilities that are usually associated only with managed switches. The built-in intelligence capabilites of the MDS108 allows it to recognize and offer packet prioritization using Zarlink Semiconductor's QoS. Packets are prioritized based upon their layer 2 VLAN priority tag or the layer 3 Type-OfService/ Differentiated Services (TOS/DS) field. This priority can be defined as transmit and/or drop priority. The MDS108 can be used to create an 8-port unmanaged switch with one WAN router port by connecting a CPU (ARM or MPC 850) to the additional MII port (port 8). The only external components needed are the physical layer transceivers and a single SBRAM, resulting in a low, total system cost. Designed to support the requirements of converging networks, the MDS108 utilizes a power conserving architecture. To further enhance this power management, the chip automatically detects when a switch port is not being utilized, and turns off the logic associated with that port, thereby saving power and reducing the current load on the switch power supply. Operating at 66 MHz internally, and with a 66 MHz interface to the external SBRAM, the MDS108 sustains full wirespeed switching on all 9 ports. The chip is packaged in a small 208 pin Plastic Quad Flat-Pak (PQFP) package. 2 Zarlink Semiconductor Inc. MDS108 MDS108 Physical Pinout LA_[6] VSS L_A[5] L_A[4] L_A[3] L_A[18] VDD L_D[31] L_D[30] L_D[29] VSS (CORE) L_D[28] L_D[27] L_D[26] VDD L_D[25] L_D[24] L_D[23] L_D[22] VSS L_D[21] L_D[20] L_D[19] L_D[18] VDD (CORE) L_D[17] L_D[16] L_D[15] VSS L_D[14] L_D[13] L_D[12] L_D[11] VDD L_D[10] L_D[9] L_D[8] VSS (CORE) L_D[7] L_D[6] L_D[5] L_D[4] VDD L_D[3] L_D[2] L_D[1] VSS L_D[0] L_A[15] VDD (CORE) L_A[16] L_ADSC# 208 206 204 202 200 198 196 194 192 190 188 186 184 182 180 178 176 174 172 170 168 166 164 162 160 158 2 4 6 8 10 12 Data Sheet L_A[7] L_A[8] VDD_CORE L_A[9] L_A[10] L_A[11] VSS L_A[12] L_A[13] L_A[14] VDD NC NC NC NC NC NC VSS (CORE) M0_TXEN M0_TXD[0] M0_TXD[1] M0_CRS_DV M0_RXD[0] M0_RXD[1] VDD M1_TXEN M1_TXD[0] M1_TXD[1] M1_CRS_DV M1_RXD[0] M1_RXD[1] VSS M2_TXEN M2_TXD[0] M2_TXD[1] M2_CRS_DV M2_RXD[0] M2_RXD[1] VDD (CORE) M3_TXEN M3_TXD[0] M3_TXD[1] M3_CRS_DV M3_RXD[0] M3_RXD[1] VSS (CORE) NC NC NC NC NC NC 156 154 152 150 148 146 144 + Pin 1 I.D. Buffer Mem Interface 14 16 142 140 138 136 134 132 130 128 126 124 20 22 24 26 28 30 32 34 36 RMII Port Interfaces 18 122 120 MII Port Interfaces 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 118 116 114 112 110 108 106 RMII Port Interfaces 98 100 102 104 L_OE# L_WE# VSS L_CLK VDD L_A[17] L_A[2] VSS SCLK VDD MIR_CTL[3] MIR_CTL[2] MIR_CTL[1] MIR_CTL[0] RSTIN# RSTOUT# VSS (CORE) T_MODE TSTOUT[7] TSTOUT[6] TSTOUT[5] TSTOUT[4] TSTOUT[3] TSTOUT[2] TSTOUT[1] TSTOUT[0] VDD (CORE) ACK DATA0 STROBE TRUNK_EN TEST# SDA SCL M_MDIO VSS M_MDC VDD M8_REFCLK VSS M8_SPEED M8_DUPLEX M8_LINK M8_TXD[3] M8_TXD[2] M8_TXD[1] M8_TXD[0] M8_TXEN VDD M8_TXCLK VSS (CORE) M8_RXD[3] NC NC NC NC NC NC VDD M4_TXEN M4_TXD[0] M4_TXD[1] M4_CRS_DV M4_RXD[0] M4_RXD[1] VSS M5_TXEN M5_TXD[0] M5_TXD[1] M5_CRS_DV M5_RXD[0] M5_RXD[1] VDD (CORE) M6_TXEN M6_TXD[0] M6_TXD[1] M6_CRS_DV M6_RXD[0] M6_RXD[1] VSS (CORE) M7_TXEN M7_TXD[0] M7_TXD[1] M7_CRS_DV M7_RXD[0] M7_RXD[1] VDD NC NC NC NC NC NC VSS M_CLK VDD (CORE) M8_RXDV M8_COL VSS M8_RXCLK VDD M8_RXD[0] M8_RXD[1] M8_RXD[2] 3 Zarlink Semiconductor Inc. Config Interfaces MDS108 Pin Reference Table Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 L_A[7] L_A[8] VDD (CORE) L_A[9] L_A[10] L_A[11] VSS L_A[12] L_A[13] L_A[14] VDD NC NC NC NC NC NC VSS (CORE) M0_TXEN M0_TXD[0] M0_TXD[1] M0_CRS_DV M0_RXD[0] M0_RXD[1] VDD M1_TXEN M1_TXD[0] M1_TXD[1] M1_CRS_DV M1_RXD[0] M1_RXD[1] VSS M2_TXEN M2_TXD[0] Pin Name 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 M2_TXD[1] M2_CRS_DV M2_RXD[0] M2_RXD[1] VDD (CORE) M3_TXEN M3_TXD[0] M3_TXD[1] M3_CRS_DV M3_RXD[0] M3_RXD[1] VSS (CORE) NC NC NC NC NC NC NC NC NC NC NC NC VDD M4_TXEN M4_TXD[0] M4_TXD[1] M4_CRS_DV M4_RXD[0] M4_RXD[1] VSS M5_TXEN M5_TXD[0] M5_TXD[1] M5_CRS_DV 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 M5_RXD[0] M5_RXD[1] Data Sheet VDD (CORE) M6_TXEN M6_TXD[0] M6_TXD[1] M6_CRS_DV M6_RXD[0] M6_RXD[1] VSS (CORE) M7_TXEN M7_TXD[0] M7_TXD[1] M7_CRS_DV M7_RXD[0] M7_RXD[1] VDD NC NC NC NC NC NC VSS M_CLK VDD (CORE) M8_RXDV/S8_CRS_DV M8_COL/S8_COL VSS M8_RXCLK/S8_RXCLK VDD M8_RXD[0]/S8_RXD M8_RXD[1] M8_RXD[2] M8_RXD[3] VSS (CORE) 4 Zarlink Semiconductor Inc. MDS108 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 M8_TXCLK/S8_TXCLK VDD M8_TXEN[0]/S8_TXEN M8_TXD[0]/S8_TXD M8_TXD[1] M8_TXD[2] M8_TXD[3] M8_LINK/S8_LINK M8_DUPLEX/S8_DUPL EX M8_SPEED VSS M8_REFCLK VDD M_MDC VSS M_MDIO SCL SDA TEST# TRUNK_ENABLE STROBE DATA0 ACK VDD (CORE) TSTOUT[0] TSTOUT[1] TSTOUT[2] TSTOUT[3] TSTOUT[4] TSTOUT[5] TSTOUT[6] TSTOUT[7] T_MODE VSS (CORE) RSTOUT# 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 RSTIN# MIRROR_CONTROL[0] MIRROR_CONTROL[1] MIRROR_CONTROL[2] MIRROR_CONTROL[3] VDD SCLK VSS L_A[2] L_A[17] VDD L_CLK VSS L_WE# L_OE# L_ADSC# L_A[16] VDD (CORE) L_A[15] L_D[0] VSS L_D[1] L_D[2] L_D[3] VDD L_D[4] L_D[5] L_D[6] L_D[7] VSS (CORE) L_D[8] L_D[9] L_D[10] VDD L_D[11] L_D[12] 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 L_D[13] L_D[14] VSS L_D[15] L_D[16] L_D[17] Data Sheet VDD (CORE) L_D[18] L_D[19] L_D[20] L_D[21] VSS L_D[22] L_D[23] L_D[24] L_D[25] VDD L_D[26] L_D[27] L_D[28] VSS (CORE) L_D[29] L_D[30] L_D[31] VDD L_A[18] L_A[3] L_A[4] L_A[5] VSS L_A[6] 5 Zarlink Semiconductor Inc. MDS108 Data Sheet Figure 2 - MDS108 Block Diagram 6 Zarlink Semiconductor Inc. MDS108 1.0 Functional Operation Data Sheet The MDS108 is designed to provide a cost-effective layer 2 switching solution, using technology from the Zarlink family to offer a highly integrated product for the unmanaged, Differentiated Services (DS) ready, Ethernet switch market. Nine 10/100 Media Access Controllers (MAC) provide the protocol interface. These MACs perform the required packet checks to ensure that each packet that is provided to the Frame Engine has met all the IEEE 802.1 standards. Each MAC supports half duplex "back pressure," and full duplex 802.3x "PAUSE" Flow Control. The PHY addresses for the 8 RMII MACs are from 08h to 0Fh. These 8 ports are denoted as ports 0 to 7. The PHY address for the uplink MAC is 10h. This port is denoted as port 8. Data packets longer than 1518 (1522 with VLAN tag) bytes and shorter than 64 bytes are dropped, and the MDS108 is designed to support minimum interframe gaps between incoming packets. The Frame Engine (FE) is the primary packet buffering and forwarding engine within the MDS108. As such, the FE controls the storage of packets into and out of the external frame buffer memory, keeps track of frame buffer availability and schedules packet transmissions. While packet data is being buffered, the FE extracts the necessary information from each packet header and sends it to the Search Engine for processing. Search results returned to the FE initiate the scheduling of packet transmission. When a packet is chosen for transmission, the FE reads the packet from external buffer memory and places it in the output FIFO of the output port. 2.0 Address Learning and Aging The MDS108 is able to begin address learning and packet forwarding shortly after power-up is completed. The Search Engine examines the contents of its internal Switch Database Memory for each valid packet that is received on a MDS108 input port. Unknown source and destination MAC addresses are detected when the Search Engine does not find a match within its database. These unknown source MAC addresses are learned by creating a new entry in the switch database memory, and storing the necessary resulting information in that location. Subsequent searches to a learned destination MAC address will return the new contents of that MAC Control Table (MCT) entry. After each source address search the MCT entry aging flag is updated. MCT entries that have not been accessed during a user configurable time period (1 to 67,108 seconds) will be removed. This aging time period can be configured using the 16-bit value stored in the register's MAC Address Aging Timer Low and High (AGETIME_LOW, AGETIME_HIGH). The aging period is defined as the bit concatenation of AGETIME_HIGH with AGETIME_LOW, multiplied by 1024 ms. For example, if AGETIME_LOW = 25, and AGETIME_HIGH = 01 (in hexadecimal), then the concatenated value 125 is equal to decimal 293. Multiplying 293 by 1024 ms, we determine that the corresponding aging time is 300 ms. In fact, 300 ms is the default aging time for the MDS108. The aging of all MCT entries is checked once during each time period. If the MCT entry has not been exercised before the end of the next time period, it will be deleted. 3.0 Quality of Service The MDS108 applies Zarlink Semiconductor's architecture to provide new QoS capabilities for unmanaged switch applications. Similar to the QoS capabilities of the other Zarlink chipset members, the MDS108 offers two transmit queues per output port. The FE manages the output transmission queues for all MDS108 ports. Once the destination address search is complete, and the switch decision is sent back to the FE, the packet is inserted into the appropriate output queue. Whether the packet is inserted into a high or low priority queue is determined by either the VLAN tag information or the Type of Service/Differentiated Services (TOS/DS) field in the IP header. Either of these priority fields can be 7 Zarlink Semiconductor Inc. MDS108 Data Sheet used to select the transmission priority (as per the USE_TOS bit in the FCR register). The mapping of the priority field values into either the high or low priority queue can be configured using the MDS108 configuration registers AVPM and TOSPM. If the system uses the TOS/DS field to prioritize packets, there are two choices regarding which bits of the TOS/DS field are used. Bits [0:2] of the TOS byte (known as the IP precedence field) or bits [3:5] of the TOS byte (known as the Delay/Throughput Reliability or (DTR) field) can be used to resolve the transmission queue priority. Either bit group, [0:2] or [3:5], can also be used to resolve packet drop precedence, as per bits 6 and 7 of the register FCBST. The MDS108 utilizes Weighted Round Robin (WRR) to schedule packets for transmission. To enable MDS108's intelligent QoS scheduling capabilities, the use of an external EEPROM to change the default register configurations is required. Weighted Round Robin is an efficient method to ensure that each of the transmission queues receives at least a minimum service level. With two output transmission queues, the MDS108 will transmit X packets from the high priority queue before transmitting a single packet from the low priority queue. The MDS108 allows the designer to set the high priority weight X to a value between 1 and 15. If both queues contain packets, and the high priority weight is set to the value 4, then the MDS108 will transmit 4 high priority packets before transmitting each low priority packet. The MDS108 also employs a proprietary mechanism to ensure the timely delivery of high priority packets. When the latency of high priority packets reaches a threshold, the MDS108 will override the WRR weights and transmit only high priority packets until the high priority packet delays are below the threshold. This threshold limit is 1 ms (last-infirst-out). The MDS108's proprietary scheduling algorithm is also designed to push low priority traffic through the device faster, if necessary, to unclog congested queues. Loading the appropriate values into the configuration registers enables the QoS scheduling capabilities of the MDS108. QoS for packet transmission is enabled by performing the following four steps: 1. Select the TOS/DS or VLAN Priority Tag field as the decision-maker for IP packet scheduling. The selection is made using bit 7 of the Flooding Control Register (FCR). FCR[7] = 0: Use VLAN Priority Tag field to determine the transmission priority, if this Tag field exists FCR[7] = 1: Use TOS/DS field for IP packet priority resolution 2. Select which TOS/DS subfield to use as the decision-maker for packet transmission priority if the TOS/DS field was selected in step 1. The selection is made using bit 6 of the FCB Buffer Low Threshold Register (FCBST). FCBST[6] = 0: Use DTR subfield to resolve the transmission priority FCBST[6] = 1: Use IP precedence subfield1 to resolve the transmission priority 3. Enable QoS using bit 5 of the Transmission Scheduling Control Register (AXSC). Set the transmission queue weight for the high priority queue using bits 0 to 3. 4. Create the mapping from the value in the TOS/DS or VLAN Priority Tag field to the corresponding high or low priority output queue. The mapping is created using the VLAN Priority Map (AVPM) and TOS Priority Map (TOSPM) registers. Note that for half duplex operation, the priority queues2 must be enabled using bit 7 in the Transmission Scheduling Control (AXSC) register to use QoS scheduling. When QoS and flow control are enabled, the MDS108 will utilize enhanced WRR to schedule packet transmission, and will use either back pressure or 802.3X flow control to handle buffer congestion. When QoS is enabled and flow control is disabled, the MDS108 will utilize enhanced WRR to schedule packet transmission, and will use Weighted Random Early Detection/Drop (WRED) to drop random packets in order to handle buffer congestion. Because of 1. IP precedence and DTR subfields are referred to as TOS/DS[0:2] and TOS/DS[3:5] in the IP TOS/DS byte. 2. In Half Duplex mode, QoS scheduling functions are disabled by default. 8 Zarlink Semiconductor Inc. MDS108 Data Sheet WRED, only a few packet flows are slowed down while the remaining see no impact from the network traffic congestion. WRED is a method of handling traffic congestion in the absence of flow control mechanisms1. When flow control is enabled, all devices that are connected to a switch node that is exercising flow control are effectively unable to transmit, including nodes that are not directly responsible for the congestion problem. This inability to transmit during flow control periods would wreak havoc with voice packets, or other high priority packet flows, and therefore flow control is not recommended for networks that mix voice and data traffic. WRED allows traffic to continue flowing into ports on a switch, and randomly drops packets with different probabilities based upon each packet's priority markings. As the switch congestion increases, the probability of dropping an incoming packet increases, and as congestion decreases, the probability of dropping an incoming packet decreases. Not surprisingly, packets designated high-drop are sacrificed with higher odds during congestion than packets designated low-drop. The following table summarizes the WRED operation of the MDS108. It lists the buffer thresholds at which each drop probability takes effect. WRED Threshold Condition for High Priority Queue Level 0 Level 1 Level 2 Condition for Low Priority Queue Drop Percentage Drop Percentage for High-Drop Packet 50% 75% 100% Drop Percentage for Low-Drop Packet 0% 25% 50% Total buffer space available in device is LPBT 24 buffers occupied 72 buffers occupied 84 buffers occupied Table 1 - WRED Operation of the MDS108 The WRED packet drop capabilities of the MDS108 are enabled by performing the following four steps: 1. Select the TOS/DS or VLAN Tag field as the decision-maker for dropping packets. The selection is made using bit 7 of the Flooding Control Register (FCR). FCR[7] = 0: Use VLAN Priority Tag field to resolve the drop level, if this field exists. FCR[7] = 1: Use TOS/DS field for IP packet drop level resolution. 2. Select which TOS/DS Tag subfield to use for dropping packets, provided that the TOS/DS field was selected in step 1. The selection is made using bit 7 of the FCB Buffer Low Threshold Register (FCBST). FCBST[7] = 0: Use DTR subfield to resolve the drop precedence. FCBST[7] = 1: Use IP precedence subfield to resolve the drop precedence. 3. Create the mapping from the values in the TOS/DS or VLAN Tag field to the packet flags representing high or low-drop precedence. The mapping is created using the VLAN Discard Map (AVDM) and TOS Discard Map (TOSDM) registers. 4. Make sure that the desired ports are flow control disabled, using the ECR1Px registers. Note that to apply the WRED QoS function of the MDS108, flow control must be disabled. 1. Flow control, of course, provides the advantage of not dropping packets. However, its primary disadvantage is that a flow controlled port may experience head-of-line blocking. This means that if even 1 packet is destined to a congested output port, then all other packets originating from the same source may, in the worst case, be delayed - even if these other packets have uncongested destinations. On the other hand, WRED may cause some packet loss, but with no such head-of-line blocking problem. Which method of handling traffic congestion should be chosen will depend on the application. 9 Zarlink Semiconductor Inc. MDS108 3.1 * Data Sheet A Few Examples No QoS Scheduling Desired At All. The default setting for the MDS108 is no QoS scheduling at all. Packets are transmitted using a simple first-in-first-out (FIFO) approach, without the reordering that would result from prioritization. All destinations use 1 queue only. QoS scheduling can be disabled for the entire chip using AXSC[5]. No QoS Scheduling Desired for Half-Duplex Ports. It is possible to disable QoS for half duplex ports in the MDS108. Indeed, this is the default setting, because it is difficult to assure quality of service for halfduplex ports, which tend to experience unpredictable delay. All destinations configured as half-duplex use 1 transmission queue only in this setting. QoS scheduling can be disabled for all half-duplex ports using AXSC[7]. QoS Scheduling for Some Destinations, But Not Others. The MDS108 does not support this feature. The three options offered are: (a) all ports are QoS-enabled, (b) no ports are QoS-enabled, and (c) only fullduplex ports are QoS enabled. Of course, the MDS108 will still exhibit single-queue scheduling at a port if all packets destined for it are marked with a single transmission priority. No Flow Control Desired. It is possible to disable flow control for the entire chip, regardless of the individual port settings. During congestion, some packets will be lost. This capability is located in AXSC[6]. Flow Control Desired for Some Sources, But Not Others. By configuring each port separately using bit 0 in the ECR1Px registers, one may enable flow control for some ports, but not others. Flow control cannot be globally disabled in AXSC[6] if this function is to be achieved. At a congested destination, an incoming packet from a flow control enabled source will trigger a flow control message sent back to that source. On the other hand, an incoming packet from a flow control disabled source may or may not be dropped, as per WRED, but will never trigger flow control. Scheduling vs. Dropping. Using the configuration registers in the MDS108, as in earlier examples, a port may or may not have flow control enabled, and a port may or may not have QoS scheduling enabled. All four combinations are permissible parameter settings, and which one is chosen depends on application. * * * * * In one common application, suppose voice, critical data and web traffic packets originate from the same set of input ports, and are destined for the same set of output ports. The MDS108's enhanced WRR scheduling can be used to ensure a delay bound for the voice packets. Furthermore, because we want to guarantee that web traffic congestion does not block critical data or voice, we must disable flow control and use WRED to intelligently drop packets. On the other hand, if the goal were file transfer without any packet dropping, one would enable the MDS108's flow control function, which halts incoming traffic when the system is congested. QoS scheduling can be disabled, both because flow control may make quality of service unpredictable, and because, in any case, delay is not critical in this application. 3.2 Port-Based Prioritization Some applications may require an explicit prioritization of packets based upon the port the packet originates from. Defining specific ports of a switch to be IP Phone ports is a specific example that makes use of MDS108's ability to assign default priorities to ports. The MDS108 can be configured to provide specific priority definitions on up to four ports (ports 0 - 3). These user defined port priorities override the packet priority markings (VLAN tag or TOS/DS), and the new priority is applied to all packets that enter the switch from that port. These port priority definitions are configured in the Port Priority (PTPRI) register. There are two bits for each of the four ports that can support port-based priorities. The EN bit allows the designer to turn on port priorities for each port, and the P bit allows the designer to select either high (1) or low (0) transmission priority for all packets that enter the switch through that port. When port priorities are enabled, the remaining ports will provide QoS based upon the VLAN Tag or TOS DS field mappings in the configuration registers. Only those ports that have port priorities enabled will override the priority mappings. 10 Zarlink Semiconductor Inc. MDS108 4.0 Buffer Management Data Sheet The MDS108 stores each input packet into the external frame buffer memory while determining the destination the packet is to be forwarded to. The total number of packets that can be stored in the frame buffer memory depends upon the size of the external SBRAM that is utilized. For a 256 KB SBRAM, the MDS108 can buffer 170 packets. For a 512 KB SBRAM, the MDS108 can buffer 340 packets. In order to provide good quality of service characteristics, the MDS108 must carefully allocate the available buffer space. Such careful allocation can be accomplished using the external EEPROM to load the appropriate values into the MDS108 configuration registers. The Low-Drop Precedence Buffer Threshold (LPBT) register assures that traffic designated as low-drop actually receives reserved buffer space. The designer can set the minimum number of buffers reserved for low-drop unicast traffic, by setting this register with a value between 0 and 255. Unreserved buffers are treated as shared, and are accessible to all types of incoming traffic. To set the maximum number of buffers permitted for all multicast packets, use the Multicast Buffer Control Register (MBCR). Unlike the LPBT register, the MBCR register does not define a reserved area of buffer memory, but instead provides a bound on the number of multicast packets that can be buffered at any one time. During operation, the MDS108 will continuously monitor the amount of frame buffer memory that is available, and when the unused buffer space falls below a designer configurable threshold, the MDS108 will initiate flow control if enabled or WRED if not. This threshold is set using the FCB Buffer Low Threshold (FCBST) register. 5.0 Virtual LANs The MDS108 provides the designer the ability to define a single port-based Virtual LAN (VLAN) for each of the nine ports. This VLAN is individually defined for each port using the Port Control Registers (ECR1Px[6:4]). Bits [6:4] allow the designer to define a VLAN ID (value between 0 - 7) for each port. When packets arrive at an input of the MDS108, the search engine will determine the VLAN ID for that port, and then determine which of the other ports are also members of that VLAN by matching their assigned VLAN ID values. The packet will then be transmitted to each port with the same VLAN ID as the source port. 6.0 Port Trunking Port trunking allows the designer to configure the MDS108, such that ports 0 and 1 are defined as a single logical port. This provides a 200 Mbps link to a switch or server utilizing two 100 Mbps ports in parallel. Ports 0 and 1 can be trunked by pulling the TRUNK_EN pin to the high state. In this mode, the source MAC addresses of all packets received from the trunk are checked against the MCT database to ensure that they have a port ID of 0 or 1. Packets that have a port ID other than 0 and 1 will cause the MDS108 to learn the new MAC address for this port change. On transmission, the trunk port is determined by hashing the source and destination MAC addresses. This provides a mapping between each MAC address and an associated trunk port. Subsequent packets with the same MAC address will always utilize the same trunk port. The MDS108 also provides a safe fail-over mode for port trunking. If one of the two ports goes down, as identified by the port's link status signal, then the MDS108 will switch all traffic over to the remaining port in the trunk. Thus, the trunk link is maintained, albeit at a lower effective bandwidth. 11 Zarlink Semiconductor Inc. MDS108 7.0 Port Mirroring Data Sheet Utilizing the 4 port mirroring control pins provides the ability to enable or disable port mirroring, select which of the remaining 7 ports is to be mirrored, and choose whether the receive or transmit data is being mirrored. The control for this function is shown in the following table. When enabled, port mirroring will allow the user to monitor traffic going through the switch on output Port 7. If the port mirroring control pins MIR_CTL[3:0] are left floating, the MDS108 will operate with the port mirroring function disabled. When port mirroring is enabled, the user must configure Port 7 to operate in the same mode as the port it is mirroring (autonegotiation, duplex, speed, flow control). Mirrored Port Port 0 RX Port 0 TX Port 1 RX Port 1 TX Port 2 RX Port 2 TX Port 3 RX Port 3 TX Port 4 RX Port 4 TX Port 5 RX Port 5 TX Port 6 RX Port 6 TX Disabled Mirror_Control [3] 1 0 1 0 1 0 1 0 1 0 1 0 1 0 X Mirror_Control [2] 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 Table 2 - Port Mirroring Configuration Mirror_Control [1] 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 Mirror_Control [0] 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 8.0 Power Saving Mode in MAC The MDS108 was designed to be power efficient. When the internal MAC sections detect that the external port is not receiving or transmitting packets, it will shut off and conserve power. When new packet data is loaded into the output transmit FIFO of a MAC in power saving mode, the MAC will return to life and begin operating immediately. When the MAC is in power saving mode and new packet data is received on the RMII, the MAC will return to life and receive data normally into the receive FIFO. This wakeup occurs when the MAC sees the Carrier Sense Data Valid (CRS_DV) signal asserted. Using this method, the switch will turn off all MAC sections during periods when there is no network activity (at night, for example), and save power. For large networks this power savings could be large. To achieve the maximum power efficiency, the designer should use a physical layer transceiver that utilizes "Wake-On-LAN" technology. 12 Zarlink Semiconductor Inc. MDS108 9.0 XLink Cascade Port Data Sheet Port 8 on the MDS108 is the XLink port. The XLink port provides a means of packet communication between two MDS108 chips. When cascaded via the XLink port, two MDS108 devices are capable of providing up to sixteen 10/100 Mbps ports. The XLink port utilizes an industry standard MII interface. This expansion port is capable of operating at several data rates, depending upon configuration. Multiple data rates are achieved by multiplying the MII reference clock for the XLink interface (M8_REFCLK). When operating at greater than 200 Mbps, the MDS108 must utilize a higher frequency system clock in order to be able to support the greater switching bandwidth requirements. With a 66 MHz system clock the MDS108 can support full wire-speed forwarding on all 8 ports, and full wire speed on the XLink port for expansion port data rates of 200 Mbps and 100 Mbps. With a 80 MHz system clock, the MDS108 can support full wire-speed operation on all 8 ports and the XLink at data rates up to 400 Mbps. The XLink frequency of operation is determined by strap options during power-up. The frame buffer memory address pins L_A[10:9] provide the frequency of operation selection as shown in the table. Xlink Data Rate 100 Mbps 200 Mbps 300 Mbps 400 Mbps L_A[10:9] Strap Level 11 10 01 00 Table 3 - XLink Port Strap Options When two MDS108 devices are cascaded to form a 16 port switch, the XLink port on each MDS108 is treated as if it were a standard switch output. Standard Ethernet packet protocols are utilized, traditional packet integrity checks are performed at the receiving MDS108 XLink port, and standard length Ethernet packets are transmitted. Refer to the XLink Application Note (MSAN-216). 10.0 EEPROM I2C Interface A simple 2 wire serial interface is provided to allow the configuration of the MDS108 from an external EEPROM. The MDS108 utilizes a 1 K bit EEPROM with an I2C interface. 13 Zarlink Semiconductor Inc. MDS108 11.0 Management Interface Data Sheet The MDS108 uses a standard parallel port interface to provide external CPU access to the internal registers. This parallel interface is composed of 3 pins: DATA0, STROBE, and ACK. The DATA0 pin provides the address and data content input to the MDS108, while the ACK pin provides the corresponding output to the external CPU. The STROBE pin is provided as the clock for both serial data streams. Any of the MDS108 internal registers can be modified through this parallel port interface1. Figure 3 - Write Command Figure 4 - Read Command Each management interface transfer consists of four parts: 1. A START pulse - occurs when DATA is sampled high when STROBE is rising followed by DATA being sampled low when STROBE falls. 2. Register address strobed into DATA0 pin, using the high level of the STROBE pin. 3. Either a read or write command (see waveforms above). 4. Data to be written provided on DATA0, or data to be read provided on ACK. Any command can be aborted in the middle by sending an ABORT pulse to the MDS108. An ABORT pulse occurs when DATA is sampled low and STROBE is rising, followed by DATA being sampled high when STROBE falls. 1. The 3-bit parallel interface is not "parallel" in the usual sense of the word; it is actually a synchronous serial architecture. However, the MDS108 management interface adheres to IEEE 1284 parallel port standards. 14 Zarlink Semiconductor Inc. MDS108 12.0 Configuration Register Definitions Data Sheet The MDS108 registers can be accessed via the parallel interface and/or the I2C interface. Some registers are only accessible through the parallel interface. The access method for each register is listed in the individual register definitions. Each register is 8 bits wide. 12.1 * * GCR - Global Control Register Access: parallel interface, Write Only Address: h30 Bit 0 Bit 1 Save configuration into EEPROM Write '1' followed by a '0' Save configuration into EEPROM and reset system Write '1' (self-clearing due to reset) Start Built-In Self-Test (BIST) Write '1' followed by a '0' Reset system Write '1' (self-clearing due to reset) Reserved (Default = 0) (Default = 0) Bit 2 Bit 3 Bit [7:4] (Default = 0) (Default = 0) 12.2 * * DCR - Device Status and Signature Register Access: parallel interface, Read Only Address: h31 Bit 0 Busy writing configuration from I2C 1: Activity 0: No Activity Busy reading configuration from I2C 1: Activity 0: No Activity Built-In Self-Test (BIST) in progress 1: BIST In-Progress 0: Normal Mode RAM error during BIST 1: RAM Error 0: No Error Reserved Revision number 00: Initial Silicon 01: Second Silicon Bit 1 Bit 2 Bit 3 Bits [5:4] Bits [7:6] 15 Zarlink Semiconductor Inc. MDS108 12.3 * * Data Sheet DA - DA Register Access: parallel interface, Read Only Address: h36 Returns 8-bit value DA (hexadecimal) if the parallel port connection is good. Otherwise, returns some other value indicating failure. 12.4 * * MBCR - Multicast Buffer Control Register Access: parallel interface and I2C, Read/Write Address: h00 Bit [7:0] MAX_CNT_LMT Maximum number of multicast frames allowed to be buffered inside the device at any one time (Default = 80) 12.5 * * FCBST - FCB BUFFER LOW THRESHOLD Access: parallel interface and I2C, Read/Write Address: h01 Bits [5:0] BUF_LOW_TH Buffer Low Threshold - the number of free buffers below which flow control or WRED is triggered Use IP precedence subfield (TOS[0:2]) for Transmission Priority Use IP precedence subfield (TOS[0:2]) for Drop Level Note that, for Bits 6 and 7, Default = 0 means to use TOS[3:5]. (Default = 3F) Bit 6 (Default = 0) Bit 7 (Default = 0) 12.6 * * LPBT - Low Drop Precedence Buffer Threshold Access: parallel interface and I2C, Read/Write Address: h02 Bits [7:0] LOW_DROP_CNT Number of frame buffers reserved for low-drop traffic (Default 3F) 16 Zarlink Semiconductor Inc. MDS108 12.7 * * Data Sheet FCR - Flooding Control Register Access: parallel interface and I2C, Read/Write Address: h03 Bits [3:0] U2MR Maximum number of flooded frames allowed within any time interval indicated by TimeBase bits (violations are discarded) 000 = 100 s 001 = 200 s 010 = 400 s 011 = 800 s 100 = 1.6 s 101 = 3.2 s 110 = 6.4 s 111 = 100 s Use TOS instead of VLAN priority for IP packet (Default = 8) Bits [6:4] TimeBase (Default = 000) Bit 7 USE_TOS (Default = 0) 12.8 * * AVTCL - VLAN Type Code Register Low Access: parallel interface and I2C, Read/Write Address: h04 Bit [7:0] VLANType_LOW Lower 8 bits of VLAN type code (Default = 00) 12.9 * * AVTCH - VLAN Type Code Register High Access: parallel interface and I2C, Read/Write Address: h05 Bit [7:0] VLANType_HIGH Upper 8 bits of VLAN type code (Default 81) 12.10 * * AVPM - VLAN Priority Map Access: parallel interface and I2C, Read/Write Address: h06 Map VLAN tag into 2 transmit queues (0 = low priority, 1 = high priority) Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Mapped priority of tag value 0 Mapped priority of tag value 1 Mapped priority of tag value 2 Mapped priority of tag value 3 Mapped priority of tag value 4 Mapped priority of tag value 5 Mapped priority of tag value 6 Mapped priority of tag value 7 (Default 0) (Default 0) (Default 0) (Default 0) (Default 0) (Default 0) (Default 0) (Default 0) 17 Zarlink Semiconductor Inc. MDS108 12.11 * * Data Sheet AVDM - VLAN Discard Map Access: parallel interface and I2C, Read/Write Address: h07 Map VLAN tag into frame discard levels (0 = low drop, 1 = high drop). Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Frame discard for tag value 0 Frame discard for tag value 1 Frame discard for tag value 2 Frame discard for tag value 3 Frame discard for tag value 4 Frame discard for tag value 5 Frame discard for tag value 6 Frame discard for tag value 7 (Default 0) (Default 0) (Default 0) (Default 0) (Default 0) (Default 0) (Default 0) (Default 0) 12.12 * * TOSPM - TOS Priority Map Access: parallel interface and I2C, Read/Write Address: h08 Map TOS field in IP packet into 2 transmit queues (0 = low priority, 1 = high priority). Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Mapped priority when TOS is 0 Mapped priority when TOS is 11 Mapped priority when TOS is 2 Mapped priority when TOS is 3 Mapped priority when TOS is 4 Mapped priority when TOS is 5 Mapped priority when TOS is 6 Mapped priority when TOS is 7 (Default 0) (Default 0) (Default 0) (Default 0) (Default 0) (Default 0) (Default 0) (Default 0) 1. TOS = 1 means the appropriate 3-bit TOS subfield is "001. 12.13 * * PTPRI - Port Priority Access: parallel interface and I2C, Read/Write Address: h09 Enable and configure port-based priorities for ports 0, 1, 2, and 3 Bit 0 Bit 1 Bit 2 Bit 3 EN0 P0 EN1 P0 Port 0: Enable; 1 = enabled Port 0: Priority; 1 = high, 0 = low Port 1: Enable; 1 = enabled Port 1: Priority; 1 = high, 0 = low (Default 0) (Default 0) (Default 0) (Default 0) 18 Zarlink Semiconductor Inc. MDS108 Bit 4 Bit 5 Bit 6 Bit 7 EN2 P2 EN3 P3 Port 2: Enable; 1 = enabled Port 2: Priority; 1 = high, 0 = low Port 3: Enable; 1 = enabled Port 3: Priority; 1 = high, 0 = low (Default 0) (Default 0) (Default 0) (Default 0) Data Sheet 12.14 * * TOSDM - TOS Discard Map Access: parallel interface and I2C, Read/Write Address: h0A Map TOS into frame discard levels (0 = low drop, 1 = high drop). Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Frame discard when TOS is 0 Frame discard when TOS is 1 Frame discard when TOS is 2 Frame discard when TOS is 3 Frame discard when TOS is 4 Frame discard when TOS is 5 Frame discard when TOS is 6 Frame discard when TOS is 7 (Default 0) (Default 0) (Default 0) (Default 0) (Default 0) (Default 0) (Default 0) (Default 0) 12.15 * * AXSC - Transmission Scheduling Control Register Access: parallel interface and I2C, Read/Write Address: h0B Bits [3:0] Bit [5] Bit [6] Transmission Queue Service Weight for high priority queue Global Quality of Service Enable Global Flow Control Disable - if 1, flow control is disabled globally; if 0, each port's flow control settings are separately configurable Half Duplex Priority Enable - if 0, priority is disabled for all half duplex ports; if 1, priority is enabled unless AXSC[5] = 0 (Default F) (Default 0) (Default 0) Bit [7] (Default 0) 12.16 * * MII_OP0 - MII Register Option 0 Access by parallel interface and I2C, Read/Write Address: h0C Permits a non-standard address for the Phy Status Register. When low and high Address bytes are 0, the MDS108 will use the standard address. Bit [7:0] Low order address byte (Default 00) 19 Zarlink Semiconductor Inc. MDS108 12.17 * * Data Sheet MII_OP1 - MII Register Option 1 Access: parallel interface and I2C, Read/Write Address: h0D Bit [7:0] High order address byte (Default 00) 12.18 * * AGETIME_LOW - MAC Address Aging Timer Low Access: parallel interface and I2C, Read/Write Address: h0E Bit [7:0] Low byte of the MAC address aging timer (Default 25) 12.19 * * AGETIME_HIGH - MAC Address Aging Timer High Access: parallel interface and I2C, Read/Write Address: h0F Bit [7:0] High byte of the MAC address aging timer. The aging time is based on the following formula: {AGETIME_HIGH, AGETIME_LOW} x 1024 ms (Default 01) The default setting provides a 300 second aging time. 12.20 * * ECR1P0 - Port 0 Control Register Access: parallel interface and I2C, Read/Write Address: h10 Bits [3:0] Bit [3] Port Mode 1 - Force configuration based on Bits [2:0] 0 - Autonegotiate and advertise based on Bits [2:0] 1 - 10 Mbps 0 - 100 Mbps 1 - Half Duplex 0 - Full Duplex 1 - Flow Control Off 0 - Flow Control On PVID Reserved Port-based VLAN ID (Default 000) (Default 0000) Bit [2] Bit [1] Bit [0] Bits [6:4] Bit [7] 20 Zarlink Semiconductor Inc. MDS108 12.21 * * Data Sheet ECR1P1 - Port 1 Control Register Access: parallel interface and I2C, Read/Write Address: h11 Bits [3:0] Bit [3] Port Mode 1 - Force configuration based on Bits [2:0] 0 - Autonegotiate and advertise based on Bits [2:0] 1 - 10 Mbps 0 - 100 Mbps 1 - Half Duplex 0 - Full Duplex 1 - Flow Control Off 0 - Flow Control On PVID Reserved Port-based VLAN ID (Default 000) (Default 0000) Bit [2] Bit [1] Bit [0] Bits [6:4] Bit [7] 12.22 * * ECR1P2 - Port 2 Control Register Access: parallel interface and I2C, Read/Write Address: h12 Bits [3:0] Bit [3] Port Mode 1 - Force configuration based on Bits [2:0] 0 - Autonegotiate and advertise based on Bits [2:0] 1 - 10 Mbps 0 - 100 Mbps 1 - Half Duplex 0 - Full Duplex 1 - Flow Control Off 0 - Flow Control On PVID Reserved Port-based VLAN ID (Default 000) (Default 0000) Bit [2] Bit [1] Bit [0] Bits [6:4] Bit [7] 12.23 * * ECR1P3 - Port 3 Control Register Access: parallel interface and I2C, Read/Write Address: h13 Bits [3:0] Port Mode (Default 0000) 21 Zarlink Semiconductor Inc. MDS108 Bit [3] 1 - Force configuration based on Bits [2:0] 0 - Autonegotiate and advertise based on Bits [2:0] 1 - 10 Mbps 0 - 100 Mbps 1 - Half Duplex 0 - Full Duplex 1 - Flow Control Off 0 - Flow Control On PVID Reserved Port-based VLAN ID (Default 000) Data Sheet Bit [2] Bit [1] Bit [0] Bits [6:4] Bit [7] 12.24 * * ECR1P4 - Port 4 Control Register Access: parallel interface and I2C, Read/Write Address: h14 Bits [3:0] Bit [3] Port Mode 1 - Force configuration based on Bits [2:0] 0 - Autonegotiate and advertise based on Bits [2:0] 1 - 10 Mbps 0 - 100 Mbps 1 - Half Duplex 0 - Full Duplex 1 - Flow Control Off 0 - Flow Control On PVID Reserved Port-based VLAN ID (Default 000) (Default 0000) Bit [2] Bit [1] Bit [0] Bits [6:4] Bit [7] 12.25 * * ECR1P5 - Port 5 Control Register Access: parallel interface and I2C, Read/Write Address: h15 Bits [3:0] Bit [3] Port Mode 1 - Force configuration based on Bits [2:0] 0 - Autonegotiate and advertise based on Bits [2:0] 1 - 10 Mbps 0 - 100 Mbps (Default 0000) Bit [2] 22 Zarlink Semiconductor Inc. MDS108 Bit [1] Bit [0] Bits [6:4] Bit [7] PVID Reserved 1 - Half Duplex 0 - Full Duplex 1 - Flow Control Off 0 - Flow Control On Port-based VLAN ID (Default 000) Data Sheet 12.26 * * ECR1P6 - Port 6 Control Register Access: parallel interface and I2C, Read/Write Address: h16 Bits [3:0] Bit [3] Port Mode 1 - Force configuration based on Bits [2:0] 0 - Autonegotiate and advertise based on Bits [2:0] 1 - 10 Mbps 0 - 100 Mbps 1 - Half Duplex 0 - Full Duplex 1 - Flow Control Off 0 - Flow Control On PVID Reserved Port-based VLAN ID (Default 000) (Default 0000) Bit [2] Bit [1] Bit [0] Bits [6:4] Bit [7] 12.27 * * ECR1P7 - PORT 7 CONTROL REGISTER Access: parallel interface and I2C, Read/Write Address: h17 Bits [3:0] Bit [3] Port Mode 1 - Force configuration based on Bits [2:0] 0 - Autonegotiate and advertise based on Bits [2:0] 1 - 10 Mbps 0 - 100 Mbps 1 - Half Duplex 0 - Full Duplex 1 - Flow Control Off 0 - Flow Control On PVID Reserved Port-based VLAN ID (Default 000) (Default 0000) Bit [2] Bit [1] Bit [0] Bits [6:4] Bit [7] 23 Zarlink Semiconductor Inc. MDS108 12.28 * * Data Sheet ECR1P8 - Port 8 Control Register Access: parallel interface and I2C, Read/Write Address: h18 Bits [3:0] Bit [3] Port Mode 1 - Force configuration based on Bits [2:0] 0 - Autonegotiate and advertise based on Bits [2:0] 1 - 10 Mbps 0 - 100 Mbps 1 - Half Duplex 0 - Full Duplex 1 - Flow Control Off 0 - Flow Control On PVID Reserved Port-based VLAN ID (Default 000) (Default 0000) Bit [2] Bit [1] Bit [0] Bits [6:4] Bit [7] 12.29 * * FC_0 - Flow Control Byte 0 Access: parallel interface and I2C, Read/Write Address: h19 The flow control hold time parameter is the length of time a flow control message is effectual (i.e. halts incoming traffic) after being received. The hold time is measured in units of "slots," the time it takes to transmit 64 bytes at wire-speed. The default setting is 32 slots, or for a 100 Mbps port, approximately 164 s. Bits [7:0] Flow control hold time byte 0 (Default FF) 12.30 * * FC_1 - Flow Control Byte 1 Access: parallel interface and I2C, Read/Write Address: h1A Bits [7:0] Flow control hold time byte 1 (Default 00) 12.31 * * FC_2 - Flow Control CRC Byte 0 Access: parallel interface and I2C, Read/Write Address: h1B Bits [7:0] Flow control frame CRC byte 0 (Default 96) 12.32 * * FC_3 - Flow Control CRC Byte 1 Access: parallel interface and I2C, Read/Write Address: h1C Bits [7:0] Flow control frame CRC byte 1 (Default 8E) 24 Zarlink Semiconductor Inc. MDS108 12.33 * * Data Sheet FC_4 - Flow Control CRC Byte 2 Access: parallel interface and I2C, Read/Write Address: h1D Bits [7:0] Flow control frame CRC byte 2 (Default 99) 12.34 * * FC_5 - Flow Control CRC Byte 3 Access: parallel interface and I2C, Read/Write Address: h1E Bits [7:0] Flow control frame CRC byte 3 (Default 9A) 12.35 * * CHECKSUM - EEPROM Checksum Access: parallel interface and I2C, Read/Write Address: h24 The calculation is [0x100 - ((sum of registers 0x00~0x23) & 0xFF)]. For example, based on the default register settings, the CHECKSUM value would be 0xEE. Bits [7:0] Checksum (Default 00) 25 Zarlink Semiconductor Inc. MDS108 13.0 MDS108 Pin Descriptions Note: # Active low signal I Input signal S Input signal with Schmitt-Trigger O Output signal OD Open-Drain driver I/O Input & Output signal SL Slew Rate Controlled D Pulldown U Pullup 5 5V Tolerance Pin No(s). Frame Buffer Memory Interface 201, 200, 199, 197, 196, 195, 193, 192, 191, 190, 188, 187, 186, 185, 183, 182, 181, 179, 178, 177, 176, 174, 173, 172, 170, 169, 168, 167, 165, 164, 163, 161 203, 151, 158, 160, 10, 9, 8, 6, 5, 4, 2, 1, 208, 206, 205, 204, 150 153 155 156 157 MII Management Interface 120 122 123 124 127 128 129 Port 0 RMII Interface 24, 23 22 21, 20 19 Port 1 RMII Interface 31, 30 29 M1_RXD[1:0] M1_CRS_DV I, U I, D Port 1 Receive Data M0_RXD[1:0] M0_CRS_DV M0_TXD[1:0] M0_TXEN I, U I, D O O Port 0 Receive Data M_MDC M_MDIO SCL SDA STROBE DATA0 ACK O I/O, U O, U, 5 MII Management Data Clock MII Management Data I/O I2C Data Clock L_D[31:0] I/O, U, SL Databus to Frame Buffer Memory Symbol Type Name & Functions Data Sheet L_A[18:2] I/O, U, SL Address pins for buffer memory L_CLK L_WE# L_OE# L_ADSC# O O, SL O O, SL Frame Buffer Memory Clock Frame Buffer Memory Write Enable Frame Buffer Memory Output Enable Frame Buffer Memory Address Status Control I2C Interface (Serial EEPROM Interface) I/O, U, OD, 5 I2C Data I/O I, U, S, 5 I, U, 5 O, U, OD, 5 Strobe Pin Data Pin Acknowledge Pin Parallel Port Management Interface Port 0 Carrier Sense and Data Valid Port 0 Transmit Data Port 0 Transmit Enable Port 1 Carrier Sense and Data Valid 26 Zarlink Semiconductor Inc. MDS108 Pin No(s). 28, 27 26 Port 2 RMII Interface 38, 37 36 35, 34 33 Port 3 RMII Interface 45,44 43 42, 41 40 Port 4 RMII Interface 65, 64 63 62, 61 60 Port 5 RMII Interface 72, 71 70 69, 68 67 Port 6 RMII Interface 79, 78 77 76, 75 74 Port 7 RMII Interface 86, 85 84 83, 82 81 Port 8 MII Interface 105, 104, 103, 102 113, 112, 111, 110 109 97 100 107 M8_RXD[3:0] M8_TXD[3:0] M8_TXEN M8_RXDV M8_RXCLK M8_TXCLK I, U O O I, D I, U I/O, U Port 8 Receive Data Port 8 Transmit Data Port 8 Transmit Enable Port 8 Receive Data Valid Port 8 Receive Clock Port 8 Transmit Clock M7_RXD[1:0] M7_CRS_DV M7_TXD[1:0] M7_TXEN I, U I, D O O Port 7 Receive Data M6_RXD[1:0] M6_CRS_DV M6_TXD[1:0] M6_TXEN I, U I, D O O Port 6 Receive Data M5_RXD[1:0] M5_CRS_DV M5_TXD[1:0] M5_TXEN I, U I, D O O Port 5 Receive Data M4_RXD[1:0] M4_CRS_DV M4_TXD[1:0] M4_TXEN I, U I, D O O Port 4 Receive Data M3_RXD[1:0] M3_CRS_DV M3_TXD[1:0] M3_TXEN I, U I, D O O Port 3 Receive Data M2_RXD[1:0] M2_CRS_DV M2_TXD[1:0] M2_TXEN I, U I, D O O Port 2 Receive Data Symbol M1_TXD[1:0] M1_TXEN O O Type Name & Functions Port 1 Transmit Data Port 1 Transmit Enable Data Sheet Port 2 Carrier Sense and Data Valid Port 2 Transmit Data Port 2 Transmit Enable Port 3 Carrier Sense and Data Valid Port 3 Transmit Data Port 3 Transmit Enable Port 4 Carrier Sense and Data Valid Port 4 Transmit Data Port 4 Transmit Enable Port 5 Carrier Sense and Data Valid Port 5 Transmit Data Port 5 Transmit Enable Port 6 Carrier Sense and Data Valid Port 6 Transmit Data Port 6 Transmit Enable Port 7 Carrier Sense and Data Valid Port 7 Transmit Data Port 7 Transmit Enable 27 Zarlink Semiconductor Inc. MDS108 Pin No(s). 114 116 115 98 118 Port 8 Serial Interface 102 100 97 110 107 109 98 114 115 Miscellaneous Control Pins 95 148 125 126 146, 145, 144, 143 142 141 Test Pins 139 TMODE# I/O, U M_CLK SCLK TEST# TRUNK_EN MIR_CTL[3:0] RESIN# RESETOUT# I I I, U I, D I/O, U I, S O Reference RMII Clock System Clock (50 - 80 MHz) Manufacturing Pin. Leave as No Connect (NC) Port Trunking Enable Port Mirroring Control Reset Pin PHY Reset Pin S8_RXD S8_RXCLK S8_CRS_DV S8_TXD S8_TXCLK S8_TXEN S8_COL S8_LINK S8_DUPLEX I, U I, U I, D O I O I, U I, U I, U Port 8 Serial Receive Data Port 8 Serial Receive Clock Symbol M8_LINK M8_SPEED M8_DUPLEX M8_COL M8_REFCLK I, U I/O, U I, U I, U I/O, U Type Name & Functions Port 8 Link Status Port 8 Speed Select (100 Mb = 1) Data Sheet Port 8 Full Duplex Select (half duplex = 0) Port 8 Collision Detect Port 8 Reference Clock Port 8 Serial Carrier Sense and Data Valid Port 8 Serial Transmit Data Port 8 Serial Transmit Clock Port 8 Serial Transmit Enable Port 8 Serial Collision Detect Port 8 Link Status Port 8 Full-Duplex Select (half duplex = 0) Manufacturing Pin. Puts device into test mode for ATE test. Leave as No Connect (NC) Test Outputs Test Outputs No Connect 138, 137, 136, 135 134, 133, 132, 131 NC Pins 12, 13, 14, 15, 16, 17, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 88, 89, 90, 91, 92, 93 Power Pins 3, 39, 73, 96, 130, 159, 184 11, 25, 59, 87, 101, 108, 119, 147, 152, 166, 175, 194, 202 18, 46, 80, 106, 140, 171, 198 7, 32, 66, 94, 99, 117, 121, 149, 154, 162, 180, 189, 207 TSTOUT[7:4] TSTOUT[3:0] N/C Reserved O I/O, U VDD (Core) VDD VSS (Core) VSS Input Input Input Input +3.3 Volt DC Supply for Core Logic (7 pins) +3.3 Volt DC Supply for I/O Pads (13 pins) Ground for Core Logic (7 pins) Ground for I/O Pads (13 pins) 28 Zarlink Semiconductor Inc. MDS108 13.1 M8_REFCLK Speed Requirement Data Sheet The M8_REFCLK pin can be either input or output pin depending on the Port 8 configuration. * * * As an output pin, its output frequency is always equal to half of the M_CLK As an input, it provides a reference clock source to the Port 8 MAC when it is configured in speed-up mode M8_REFCLK input frequency is equal to 25% of the Port 8 speed (data rate) Port 8 Configuration Mode Reg. 2x 3x 4x Speed 10/100 M 200 M 300 M 400 M M8_REFCLK Input/Output Output Input Input Input M_CLK/2 50 MHz 75 MHz 100 MHz Freq. 29 Zarlink Semiconductor Inc. MDS108 13.2 Strap Options Data Sheet The Strap options are relevant during the initial power-on period, when reset is asserted. During reset, the MDS108 will examine the boot strap address pin to determine its value and modify the internal configuration of the chip accordingly. "1" mean Pull-up "0" means Pull-down with an external 1 K Ohm. Default value is 1, (all boot strap pins have internal pull up resistor). Pin No(s). Boot Strap Pins 206 (L_A[5]) 208 (L_A [6]) 5, 4 (L_A [10:9]) Symbol Memory Size EEPROM XLINK Speed Name & Functions 1 - Memory size = 256 KB 0 - Memory size = 512 KB 1 - NO EEPROM Installed 0 - EEPROM Installed1 11 - 100 Mbps 10 - 200 Mbps 01 - 300 Mbps 00 - 400 Mbps (0 - Pull down, 1 - Pull up) 1 - MII Mode for port 8 0 - Serial Mode for port 8 Link Polarity for serial interface 1 - Active Low 0 - Active High Full/Half Duplex Polarity for serial interface 1 - Active Low 0 - Active High Speed polarity for serial interface 1 - Active Low 0 - Active High Use in cascade mode only For Board/System Manufacturing Test2 1 - Disable 0 - Enable 151 (L_A[17]) 150 (L_A[2]) Port 8 MII/Serial Link Polarity 204 (L_A[3]) FDX Polarity 205 (L_A[4]) SPD100 Polarity 2 (L_A[8]) 133 (TST[2]) Device ID SBRAM Self Test Note 1: If the MDS108AL is configured from EEPROM preset (L_A[6] pulled down at reset), it will try to load its configuration from the EEPROM. If the EEPROM is blank or not preset, it will not boot up. The parallel port can be used to program the EEPROM at any time. During normal power-up, the MDS108 will run through an external SBRAM memory test to ensure that there are no memory interface problems. If a problem is detected, the chip will stop functioning. To facilitate board debug in the event that a system stops functioning, the MDS108AL can be put into a continuous SBRAM self test mode to allow an operator to determine if there are stuck pins in the memory interface (using network analyzer). Note 2: 30 Zarlink Semiconductor Inc. MDS108 14.0 14.1 Data Sheet Characteristics and Timing Absolute Maximum Rating -65C to +150C -40C to +85C +125C +3.0 V to +3.6 V -0.5 V to (VDD +3.3 V) -0.5V to (VDD +0.3 V) Storage Temperature Operating Temperature Maximum Junction Temperature Supply Voltage VDD with Respect to VSS Voltage on 5V Tolerant Input Pins Voltage on Other Pins Caution: Stresses above those listed may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to the absolute Maximum Ratings for extended Ratings for extended periods may affect device reliability. 14.2 14.3 DC Electrical Characteristics Recommended Operating Conditions Parameter Description Frequency of Operation Supply Current - @ 55 MHz, 8x100M, 100% Full Duplex Traffic (VDD = 3.3V) Output High Voltage (CMOS) Output Low Voltage (CMOS) Input High Voltage (TTL 5 V tolerant) Input Low Voltage (TTL 5 V tolerant) Input Leakage Current (0.1 V < VIN < VDD) (all pins except those with internal pull-up/ pulldown resistors) Output Leakage Current (0.1 V < VOUT < VDD) Input Capacitance Output Capacitance I/O Capacitance Thermal resistance with 0 air flow Thermal resistance with 1 m/s air flow Thermal resistance with 2 m/s air flow Thermal resistance between junction and case 2.4 0.4 2.0 VDD + 2.0 0.8 10 Min. 50 Typ. 66 580 Max. 80 Unit MHz mA V V V V A fOSC IDD VOH VOL VDD = 3.0V to 3.6V (3.3v +/- 10%) TAMBIENT = -40C to +85 C Symbol VIH - TTL VIL-TTL IIL IOL CIN COUT CI/O ja ja ja jc 10 5 5 7 29.7 28.8 26.8 12.6 A pF pF pF C/W C/W C/W C/W 31 Zarlink Semiconductor Inc. MDS108 14.4 Clock Frequency Specifications Parameter SCLK - Core System Clock Input M_CLK - RMII Port Clock M8_REFCLK - MII Reference Clock L_CLK - Frame Buffer Memory Clock M_MDC - MII Management Data Clock SCL - I C Data Clock 2 Data Sheet Symbol C1 C2 C3 C4 C5 C6 (Hz) 50 M 50 M 25 M 50 M 1.56 M 50 K Note: L_CLK = SCLK M_MDC = SCLK/32 SCL = M_CLK/1000 Suggestion Clock rate for various configurations: Input Configuration Port 0-7 10 M RMII 100 M RMII 100 M RMII 100 M RMII 100 M RMII 100 M RMII Port 8 10/100 M MII Not Used 10/100 M MII 200 M MII 300 M MII 400 M MII SCLK 50 M 55 M 60 M 66.66 M 75 M 80 M M_CLK (RMII) 50 M 50 M 50 M 50 M 50 M 50 M M8_REF ---50 M 75 M 100 M L_CLK =SCLK =SCLK =SCLK =SCLK =SCLK =SCLK Output M_MDC =SCLK/32 =SCLK/32 =SCLK/32 =SCLK/32 =SCLK/32 =SCLK/32 SCL 50 K 50 K 50 K 50 K 50 K 50 K 32 Zarlink Semiconductor Inc. MDS108 14.5 14.5.1 AC Timing Characteristics Frame Buffer Memory Interface: Data Sheet L_D[31:0] Figure 5 - Frame Buffer Memory Interface Symbol L1 L2 L3 L4 L6 L8 L9 Parameter L_D[31:0] input setup time L_D[31:0] input hold time L_D[31:0] output valid delay L_A[18:2] output valid delay L_ADSC# output valid delay L_WE# output valid delay L_OE# output valid delay 50 MHz Min. (ns) 5 0 1 1 1 1 1 8 8 8 8 8 Max. (ns) Note CL = 30 pF CL = 50 pF CL = 50 pF CL = 30 pF CL = 30 pF Table 4 - Frame Buffer Memory Interface Timing 33 Zarlink Semiconductor Inc. MDS108 14.6 RMII Timing Requirements Symbol M1 M2 M3 M4 M5 M6 M7 M_CLK M[7:0]_RXD[1:0] input setup time M[7:0]_RXD[1:0] input hold time M[7:0]_CRS_DV input setup time M[7:0]_TXEN output delay time M[7:0]_TXD[1:0] output delay time M[7:0]_LINK input setup time 4 1 4 1 1 4 11 11 CL = 30 pF CL = 30 pF Parameter 50 MHz Min. (ns) Max. (ns) Note: Data Sheet Reference Input Clock Table 5 - RMII Timing Requirements 14.7 MII Timing Requirements Figure 6 - Transmit Timing Time Min. 5 5 5 5 25 25 Max. 20 20 20 20 Inf. Inf. 5 5 Symbol 1 2 3 4 5 6 Parameter M8_TXCLK rise to M8_TXD[3:0] inactive delay M8_TXCLK rise to M8_TXD[3:0] active delay M8_TXCLK rise to M8_TXEN active delay M8_TXCLK rise of last M8_TXD bit to M8_TXEN inactive delay M8_TXCLK High wide M8_TXCLK Low wide M8_TXCLK input rise time require M8_TXCLK input fall time require Unit ns ns ns ns ns ns ns ns *Inf. = infinite Table 6 - Transmit Timing Requirements 34 Zarlink Semiconductor Inc. MDS108 Data Sheet Figure 7 - Receive Timing Symbol 1 2 3 4 5 6 7 8 9 10 Parameter M8_RXD[3:0] Low input setup time M8_RXD[3:0] Low input hold time M8_RXD[3:0] High input setup time M8_RXD[3:0] High input hold time M8_RXDV Low input setup time M8_RXDV Low input hold time M8_RXDV High input setup time M8_RXDV High input hold time M8_RXCLK High wide M8_RXCLK Low wide M8_RXCLK input rise time require M8_RXCLK input fall time require Time Min. 10 5 10 5 10 5 10 5 25 25 Inf. Inf. 5 5 Max. Unit ns ns ns ns ns ns ns ns ns ns ns ns Table 7 - Receive Timing Requirements 35 Zarlink Semiconductor Inc. D D1 = 0-7 A A2 A1 E1 E L INDEX CORNER PIN 1 Notes: 1. Pin 1 indicator may be a corner chamfer, dot or both. 2. Controlling dimensions are in millimeters. 3. The top package body size may be smaller than the bottom package body size by a max. of 0.15 mm. 4. Dimension D1 and E1 do not include mould protusion. c Zarlink Semiconductor 2003 All rights reserved. Package Code Previous package codes: ISSUE ACN DATE APPRD. For more information about all Zarlink products visit our Web Site at www.zarlink.com Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively "Zarlink") is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use. Neither the supply of such information or purchase of product or service conveys any license, either express or implied, under patents or other intellectual property rights owned by Zarlink or licensed from third parties by Zarlink, whatsoever. Purchasers of products are also hereby notified that the use of product in certain ways or in combination with Zarlink, or non-Zarlink furnished goods or services may infringe patents or other intellectual property rights owned by Zarlink. This publication is issued to provide information only and (unless agreed by Zarlink in writing) may not be used, applied or reproduced for any purpose nor form part of any order or contract nor to be regarded as a representation relating to the products or services concerned. The products, their specifications, services and other information appearing in this publication are subject to change by Zarlink without notice. No warranty or guarantee express or implied is made regarding the capability, performance or suitability of any product or service. Information concerning possible methods of use is provided as a guide only and does not constitute any guarantee that such methods of use will be satisfactory in a specific piece of equipment. It is the user's responsibility to fully determine the performance and suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not been superseded. Manufacturing does not necessarily include testing of all functions or parameters. These products are not suitable for use in any medical products whose failure to perform may result in significant injury or death to the user. All products and materials are sold and services provided subject to Zarlink's conditions of sale which are available on request. Purchase of Zarlink's I2C components conveys a licence under the Philips I2C Patent rights to use these components in and I2C System, provided that the system conforms to the I2C Standard Specification as defined by Philips. Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright Zarlink Semiconductor Inc. All Rights Reserved. TECHNICAL DOCUMENTATION - NOT FOR RESALE |
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